众核网络处理器下 IPSec V PN 系统设计与实现
TP311.5; 针对网络带宽的不断增加及数据包在网络传输过程中的安全问题，借助众核网络处理器作为硬件平台，设计一种基于IPSec V PN技术的加解密系统，介绍了数据包的获取和负载均衡、数据包的封装格式及加解密方式的设计过程。同时实现了基于 Tilera众核网络处理器的IPSec V PN系统，满足对数据包的并行处理。实验结果表明，对于不同大小负载的数据包，系统均满足10Gbps的加解密处理能力。...
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| Published in | 西安工程大学学报 Vol. 30; no. 2; pp. 230 - 235 |
|---|---|
| Main Authors | , , |
| Format | Journal Article |
| Language | Chinese |
| Published |
西安工程大学计算机科学学院,陕西西安,710048
2016
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| Subjects | |
| Online Access | Get full text |
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| Abstract | TP311.5; 针对网络带宽的不断增加及数据包在网络传输过程中的安全问题，借助众核网络处理器作为硬件平台，设计一种基于IPSec V PN技术的加解密系统，介绍了数据包的获取和负载均衡、数据包的封装格式及加解密方式的设计过程。同时实现了基于 Tilera众核网络处理器的IPSec V PN系统，满足对数据包的并行处理。实验结果表明，对于不同大小负载的数据包，系统均满足10Gbps的加解密处理能力。 |
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| AbstractList | TP311.5; 针对网络带宽的不断增加及数据包在网络传输过程中的安全问题，借助众核网络处理器作为硬件平台，设计一种基于IPSec V PN技术的加解密系统，介绍了数据包的获取和负载均衡、数据包的封装格式及加解密方式的设计过程。同时实现了基于 Tilera众核网络处理器的IPSec V PN系统，满足对数据包的并行处理。实验结果表明，对于不同大小负载的数据包，系统均满足10Gbps的加解密处理能力。 |
| Abstract_FL | For increasing network bandwidth and the security of packets in the network trans‐mission process ,an encryption and decryption system based on IPSec VPN is designed by multi‐core network processor .In addition ,the capture and load balance of packets ,the format of packets and the encryption and decryption mode are introduced .Meanwhile ,the IPSec VPN system based on Tilera Multi‐core network processor is realized ,which meets the parallel pro‐cessing of the data packets .Experimental results show that the encryption and decryption sys‐tem with different sizes can meet the encryption and decryption processing capability of 10Gbps . |
| Author | 王建 陈亮 胡康 |
| AuthorAffiliation | 西安工程大学计算机科学学院,陕西西安,710048 |
| AuthorAffiliation_xml | – name: 西安工程大学计算机科学学院,陕西西安,710048 |
| Author_FL | CHEN Liang HU Kang WANG Jian |
| Author_FL_xml | – sequence: 1 fullname: WANG Jian – sequence: 2 fullname: CHEN Liang – sequence: 3 fullname: HU Kang |
| Author_xml | – sequence: 1 fullname: 王建 – sequence: 2 fullname: 陈亮 – sequence: 3 fullname: 胡康 |
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| ClassificationCodes | TP311.5 |
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| Copyright | Copyright © Wanfang Data Co. Ltd. All Rights Reserved. |
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| DocumentTitle_FL | Design and implementation of IPSec VPN system based on multi-core network processor |
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| Keywords | multi-core parallel computation 众核处理器 network security IPSec VPN 网络安全 并行计算 |
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| Snippet | TP311.5; 针对网络带宽的不断增加及数据包在网络传输过程中的安全问题，借助众核网络处理器作为硬件平台，设计一种基于IPSec V PN技术的加解密系统，介绍了数据包的获取和负载均衡、数据包的封装格式及加解密方式的设计过程。同时实现了基于 Tilera众核网络处理器的IPSec V... |
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| Title | 众核网络处理器下 IPSec V PN 系统设计与实现 |
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