Dummy pattern design for reducing device performance drift

• Main Authors: Lu, Lee-Chung, Kuo, Chien-Chih, Li, Jian-Yi, Yang, Sheng-Jier
• Format: Patent
• Language: English
• Published: 08.01.2013

A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. A structure includes a target diffusion region including a first edge with a first length and a second edge with a second edge perpendicular to the first length. A first stress-blocking dummy diffusion region is adjacent to the first edge, with no dummy diffusions regions therebetween. A second stress-blocking dummy diffusion region is adjacent to the second edge, with no dummy diffusion regions therebetween.