Delay circuit and method for delaying signal
A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or mor...
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| Main Authors | , , |
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| Format | Patent |
| Language | English |
| Published |
01.01.2013
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| Online Access | Get full text |
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| Summary: | A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. |
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