Address delay circuit of semiconductor memory apparatus

An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output int...

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Main Authors Ko, Jae Bum, Lee, Jong Chern
Format Patent
LanguageEnglish
Published 25.12.2012
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Abstract An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.
AbstractList An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.
Author Lee, Jong Chern
Ko, Jae Bum
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References Konishi et al. (5384745) 19950100
(2002-025275) 20020100
(100672128) 20070100
(2009-187670) 20090800
(2007-066517) 20070300
La (2002/0048197) 20020400
(1020070035928) 20070400
Kim (6590828) 20030700
Kim et al. (7529140) 20090500
Origasa et al. (6349072) 20020200
Jeong (2008/0056033) 20080300
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