Address delay circuit of semiconductor memory apparatus

An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output int...

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Bibliographic Details
Main Authors Ko, Jae Bum, Lee, Jong Chern
Format Patent
LanguageEnglish
Published 25.12.2012
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Summary:An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.