Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)

Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before appl...

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Bibliographic Details
Main Authors Baars, Peter, Lepper, Marco, Fitz, Clemens
Format Patent
LanguageEnglish
Published 23.10.2012
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Summary:Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.