Optimal channel design for memory devices for providing a high-speed memory interface

A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller an...

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Bibliographic Details
Main Authors Wang, Min, Ferolito, Philip Arnold, Rajan, Suresh Natarajan, Smith, Michael John Sebastian
Format Patent
LanguageEnglish
Published 02.10.2012
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Summary:A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.