Memory controllers, memory systems, solid state drives and methods for processing a number of commands

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host comm...

Full description

Saved in:
Bibliographic Details
Main Authors Asnaashari, Mehdi, Liao, Yu-Song, Yang, Jui-Yao, Nemazie, Siamack
Format Patent
LanguageEnglish
Published 04.09.2012
Online AccessGet full text

Cover

More Information
Summary:The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.