Disturb-free static random access memory cell

A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line,...

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Bibliographic Details
Main Authors Chuang, Ching-Te, Yang, Hao-I, Lin, Jihi-Yu, Yang, Shyh-Chyi, Tu, Ming-Hsien, Hwang, Wei, Jou, Shyh-Jye, Lee, Kun-Ti, Li, Hung-Yu
Format Patent
LanguageEnglish
Published 04.09.2012
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Summary:A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.