Verifying multiple constraints for circuit designs

Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is...

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Bibliographic Details
Main Authors Ku, Shan-Chyun, Glusman, Marcelo, Hsieh, Yee-Wing, Pandey, Manish, Krstic, Angela, Kirihennedige, Sarath
Format Patent
LanguageEnglish
Published 26.06.2012
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Summary:Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.