Method of forming metal/high-κ gate stacks with high mobility

10 2 212 2 The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of...

Full description

Saved in:
Bibliographic Details
Main Authors Andreoni, Wanda, Callegari, Alessandro C, Cartier, Eduard A, Curioni, Alessandro, D'Emic, Christopher P, Gousev, Evgeni, Gribelyuk, Michael A, Jamison, Paul C, Jammy, Rajarao, Lacey, Dianne L, McFeely, Fenton R, Narayanan, Vijay, Pignedoli, Carlo A, Shepard, Jr, Joseph F, Zafar, Sufi
Format Patent
LanguageEnglish
Published 10.04.2012
Online AccessGet full text

Cover

More Information
Summary:10 2 212 2 The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0×10inversion charges/cmor greater.