Work function engineering for eDRAM MOSFETs

Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, a...

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Bibliographic Details
Main Authors Chen, Xiangdong, Ho, Herbert L, Wang, Geng
Format Patent
LanguageEnglish
Published 06.03.2012
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Summary:Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.