Microarchitecture, method and computer program product for efficient data gathering from a set of trace arrays

An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data se...

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Bibliographic Details
Main Authors West, Jr, Patrick M, Bartik, Jane H, Recktenwald, Martin, Shum, Chung-Lung K, Swaney, Scott B
Format Patent
LanguageEnglish
Published 28.02.2012
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Summary:An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided.