Self test apparatus for identifying partially defective memory

• Main Authors: Huott, William V, Lund, David J, Marz, Kenneth H, Mechtly, Bryan L, Patel, Pradip
• Format: Patent
• Language: English
• Published: 08.11.2011

A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST...