Self test apparatus for identifying partially defective memory

A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST...

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Main Authors Huott, William V, Lund, David J, Marz, Kenneth H, Mechtly, Bryan L, Patel, Pradip
Format Patent
LanguageEnglish
Published 08.11.2011
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Abstract A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
AbstractList A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
Author Huott, William V
Patel, Pradip
Marz, Kenneth H
Lund, David J
Mechtly, Bryan L
Author_xml – sequence: 1
  givenname: William V
  surname: Huott
  fullname: Huott, William V
– sequence: 2
  givenname: David J
  surname: Lund
  fullname: Lund, David J
– sequence: 3
  givenname: Kenneth H
  surname: Marz
  fullname: Marz, Kenneth H
– sequence: 4
  givenname: Bryan L
  surname: Mechtly
  fullname: Mechtly, Bryan L
– sequence: 5
  givenname: Pradip
  surname: Patel
  fullname: Patel, Pradip
BookMark eNrjYmDJy89L5WSwC07NSVMoSS0uUUgsKEgsSiwpLVZIyy9SyExJzSvJTKvMzEtXAIqXZCbm5FQqpKSmpSaXZJalKuSm5uYXVfIwsKYl5hSn8kJpbgYFN9cQZw_d0uKCxBKgCcXx6UWJIMrAwsDU1NLMwJgIJQBq-jPJ
ContentType Patent
CorporateAuthor International Business Machines Corporation
CorporateAuthor_xml – name: International Business Machines Corporation
DBID EFH
DatabaseName USPTO Issued Patents
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EFH
  name: USPTO Issued Patents
  url: http://www.uspto.gov/patft/index.html
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
ExternalDocumentID 08055960
GroupedDBID EFH
ID FETCH-uspatents_grants_080559603
IEDL.DBID EFH
IngestDate Mon Mar 06 19:17:59 EST 2023
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-uspatents_grants_080559603
OpenAccessLink https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8055960
ParticipantIDs uspatents_grants_08055960
PatentNumber 8055960
PublicationCentury 2000
PublicationDate 20111108
PublicationDateYYYYMMDD 2011-11-08
PublicationDate_xml – month: 11
  year: 2011
  text: 20111108
  day: 08
PublicationDecade 2010
PublicationYear 2011
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References_xml – year: 19910200
  ident: 4992984
  contributor:
    fullname: Busch et al.
– year: 20010400
  ident: 6222211
  contributor:
    fullname: Chen
– year: 19890100
  ident: 1014797
– year: 19991200
  ident: 6006311
  contributor:
    fullname: Arimilli et al.
– year: 20040500
  ident: 2004/0088603
  contributor:
    fullname: Asher et al.
– year: 20000900
  ident: 6125465
  contributor:
    fullname: McNamara et al.
– year: 19850600
  ident: 4523313
  contributor:
    fullname: Nibby, Jr. et al.
– year: 20050700
  ident: 6918071
  contributor:
    fullname: Cherabuddi et al.
– year: 19911200
  ident: 5070502
  contributor:
    fullname: Supnik
– year: 20051000
  ident: 6954827
  contributor:
    fullname: Park et al.
– year: 19990900
  ident: 5953745
  contributor:
    fullname: Lattimore et al.
– year: 20020200
  ident: 6351789
  contributor:
    fullname: Green
– year: 19990900
  ident: 5958068
  contributor:
    fullname: Arimilli et al.
– year: 19980900
  ident: 5805789
  contributor:
    fullname: Huott et al.
– year: 19981100
  ident: 5835502
  contributor:
    fullname: Aipperspach et al.
– year: 20030500
  ident: 2003/0088811
  contributor:
    fullname: Cherabuddi et al.
– year: 20031200
  ident: 6671644
  contributor:
    fullname: Huismann et al.
– year: 20010100
  ident: 6173357
  contributor:
    fullname: Ju
– year: 20040400
  ident: 6720652
  contributor:
    fullname: Akram et al.
– year: 19950100
  ident: 0632380
– year: 20031200
  ident: 6671822
  contributor:
    fullname: Asher et al.
– year: 20040100
  ident: 6675319
  contributor:
    fullname: Chen
– year: 19970800
  ident: 5659551
  contributor:
    fullname: Huott et al.
– year: 19981100
  ident: 5835504
  contributor:
    fullname: Balkin et al.
Score 2.8237867
Snippet A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable...
SourceID uspatents
SourceType Open Access Repository
Title Self test apparatus for identifying partially defective memory
URI https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8055960
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfVxLSwMxEB5qEdSTomJ9kYPX6Oo-0ly8iMsiKAUVeivT7ESE7XbpZpH-eydZKV70FhKYDBky833DzABcxdbYNNMkI8zQt-QoiQmSLMlogzpVKhDF55eseE-epul0AMWmF2bB30g2rEt73bWNW4biSnbvveFlP_zZzwis_fSBr7paYjkp7c04YmycMXnf4pWHRXmxBzssgiFb7dpfQSPfh-1J2D2AAdWHcP9KlRWM7JzAJkzc7lrBkFF8hl7Z0G8kGm9JrKq1KMn2vkgsfDHs-ghE_vj2UMjNZbOPlS9imUU_SsXHMGQyTycgSKcxYyKDScnESN_iXWyJ5nasDAdupUYw-lPM6T9nZ7Absp0h4XkOQ7fq6ILDpZtfhrf4Bsnvdys
link.rule.ids 230,309,783,805,888,64374
linkProvider USPTO
linkToPdf http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfVxLT8MwDLamgXicQIAYzxy4Bgp9ZL1wgVXlNVUCpN2qLHUQUtdVayq0f4-TookLXBPJsWLF_uzYH8CFr5UOoxi5JyNpR3IEl4FEXqCKlYxDIVyi-DKO0vfgcRJOepCuZmFm9Ix4Tbo0l21Tm7lrriT33hmed-TPliOwsuwDX1U5l0VW6KuhR9g4ouR9zX5FWRb9UZJuwyYJIdBWmeZX2Eh2YD1zq7vQw2oPbl-x1IywnWGydpzbbcMINLJPNy3rJo5YbW0py3LJCtSdN2Iz2w673AeWjN7uUr46LP9Y2DaW3PtRyz-APqXzeAgM49AnVKRkUFBqFF_LG18jTvVQKArdQgxg8KeYo3_2zmEju0_y54fx0zFsudKnq36eQN8sWjyl2GmmZ-5avgHMDXom
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Self+test+apparatus+for+identifying+partially+defective+memory&rft.inventor=Huott%2C+William+V&rft.inventor=Lund%2C+David+J&rft.inventor=Marz%2C+Kenneth+H&rft.inventor=Mechtly%2C+Bryan+L&rft.inventor=Patel%2C+Pradip&rft.number=8055960&rft.date=2011-11-08&rft.externalDBID=n%2Fa&rft.externalDocID=08055960