Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability
By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK materi...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
19.07.2011
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| Online Access | Get full text |
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| Summary: | By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies. |
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