Nonvolatile memory element array with storing layer formed by resistance variable layers

A lower electrode is provided on a semiconductor chip substrate. A lower electrode is covered with a first interlayer insulating layer from above. A first contact hole is provided on the lower electrode to penetrate through the first interlayer insulating layer. A low-resistance layer forming the re...

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Bibliographic Details
Main Authors Mikawa, Takumi, Takagi, Takeshi, Kawashima, Yoshio, Arita, Koji
Format Patent
LanguageEnglish
Published 14.06.2011
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Summary:A lower electrode is provided on a semiconductor chip substrate. A lower electrode is covered with a first interlayer insulating layer from above. A first contact hole is provided on the lower electrode to penetrate through the first interlayer insulating layer. A low-resistance layer forming the resistance variable layer is embedded to fill the first contact hole. A high-resistance layer is provided on the first interlayer insulating layer and the low-resistance layer. The resistance variable layer is formed by a multi-layer resistance layer including a single layer of the high-resistance layer and a single layer of the low-resistance layer. The low-resistance layer forming the memory portion is isolated from at least its adjacent memory portion.