Dynamic critical path detector for digital logic circuit paths

Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating...

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Bibliographic Details
Main Authors Bueti, Serafino, Goodnow, Kenneth J, Leonard, Todd E, Mann, Gregory J, Sandon, Peter A, Twombly, Peter A, Woodruff, Charles S
Format Patent
LanguageEnglish
Published 10.05.2011
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Summary:Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.