Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
A thin film transistor (TFT) array panel that includes a substrate, a gate wire including a gate pad, a gate insulating layer pattern, a semiconductor layer pattern, an ohmic contact layer pattern, a data wire including a data pad and a drain electrode, and a passivation layer pattern is presented....
Saved in:
| Main Authors | , |
|---|---|
| Format | Patent |
| Language | English |
| Published |
15.02.2011
|
| Online Access | Get full text |
Cover
Loading…
| Summary: | A thin film transistor (TFT) array panel that includes a substrate, a gate wire including a gate pad, a gate insulating layer pattern, a semiconductor layer pattern, an ohmic contact layer pattern, a data wire including a data pad and a drain electrode, and a passivation layer pattern is presented. The passivation layer pattern is formed on the data wire and has contact holes exposing the gate pad, the data pad, and the drain electrode. The passivation layer pattern also has a planar shape that is similar that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire. A pixel electrode is electrically connected to the exposed portion of the drain electrode and contacts the gate insulating layer pattern. |
|---|