Semiconductor memory device having advanced tag block

A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded addres...

Full description

Saved in:
Bibliographic Details
Main Authors Hong, Sang-Hoon, Ahn, Jin-Hong, Ko, Jae-Bum, Kim, Se-Jun
Format Patent
LanguageEnglish
Published 11.01.2011
Online AccessGet full text

Cover

More Information
Summary:A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.