Circuit for locking a delay locked loop (DLL) and method therefor

A receive circuit includes a DLL core, a latch, and a DLL control circuit. The DLL core has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch has a signal input for receiving an...

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Bibliographic Details
Main Authors Searles, Shawn, Syed, Faisal A, Humphries, Nicholas T
Format Patent
LanguageEnglish
Published 11.01.2011
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Summary:A receive circuit includes a DLL core, a latch, and a DLL control circuit. The DLL core has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core, and an output for providing an internal data signal. The DLL control circuit provides the DLL clock signal to the first input of the DLL core responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core responsive to a processor clock signal while the receive circuit is in a second mode.