Structure for task based debugger (transaction-event-job-trigger)
Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that link...
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Format | Patent |
Language | English |
Published |
26.10.2010
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Abstract | Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events. |
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AbstractList | Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events. |
Author | Leonard, Todd E Goodnow, Kenneth J Mann, Gregory J Woodruff, Charles S Bueti, Serafino |
Author_xml | – sequence: 1 givenname: Serafino surname: Bueti fullname: Bueti, Serafino – sequence: 2 givenname: Kenneth J surname: Goodnow fullname: Goodnow, Kenneth J – sequence: 3 givenname: Todd E surname: Leonard fullname: Leonard, Todd E – sequence: 4 givenname: Gregory J surname: Mann fullname: Mann, Gregory J – sequence: 5 givenname: Charles S surname: Woodruff fullname: Woodruff, Charles S |
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References | Douskey et al. (6115763) 20000900 Matthews et al. (6430707) 20020800 Bueti et al. (2008/0127216) 20080500 Kang et al. (2005/0193276) 20050900 Oberlaender (2005/0102572) 20050500 Rajsuman et al. (6678645) 20040100 Brinson et al. (7434182) 20081000 Liu et al. (5425036) 19950600 Mann, et al., U.S. Appl. No. 11/461,793, BUR920060036US1, Office Action Communication, Nov. 6, 2008, 12 Pages. Barkataki et al. (6332210) 20011200 Yee (2005/0193254) 20050900 Bueti, et al., U.S. Appl. No. 11/461,793, BUR920060036US1, Office Action Communication, May 5, 2009, 11 Pages. Wang et al. (2004/0254779) 20041200 Swoboda et al. (6567933) 20030500 Kimmelman et al. (7444546) 20081000 Barry et al. (2008/0222333) 20080900 Songer et al. (7080283) 20060700 |
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Snippet | Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for... |
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