Method and system for response determinism by synchronization

A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facili...

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Main Authors Navada, Muraleedhara H, Frodsham, Tim, Dabral, Sanjay, Baum, Allen, Matthews, Chris D, Gianos, Chris C, Shah, Rahul R, Schoenborn, Theodore Z
Format Patent
LanguageEnglish
Published 28.09.2010
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Summary:A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.