Method and apparatus of stress relief in semiconductor structures

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar...

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Bibliographic Details
Main Authors Hoinkis, Mark, Hierlemann, Matthias, Friese, Gerald, Cowley, Andy, Warner, Dennis J, Kaltalioglu, Erdem
Format Patent
LanguageEnglish
Published 31.08.2010
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Summary:A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.