Chip package structure and circuit board thereof
A chip package structure including a substrate, a circuit layer, a solder mask, a chip, and an encapsulant is provided. The circuit layer is disposed on the substrate and includes two traces and a dummy trace. The dummy trace is disposed between the traces. The solder mask covers the circuit layer a...
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| Main Author | |
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| Format | Patent |
| Language | English |
| Published |
17.08.2010
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| Online Access | Get full text |
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| Summary: | A chip package structure including a substrate, a circuit layer, a solder mask, a chip, and an encapsulant is provided. The circuit layer is disposed on the substrate and includes two traces and a dummy trace. The dummy trace is disposed between the traces. The solder mask covers the circuit layer and the substrate. The chip is disposed on the solder mask and electrically connected to the traces. The encapsulant covers the solder mask and wraps the chip. The traces and the dummy trace extend from the inside of the area covered by the encapsulant to the outside of the area covered by the encapsulant. Because the dummy trace is used in the chip package structure, it can be avoided that the traces is pulled apart when the redundant encapsulant is removed after the encapsulant is formed. |
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