Method to control core duty cycles using low power modes

A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer...

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Bibliographic Details
Main Author Fleming, Bruce L
Format Patent
LanguageEnglish
Published 10.08.2010
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Summary:A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer in response to the interrupt other than a timer tick interrupt.