Signal processing apparatus
The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f calculates (the count value IC+the Carry+t...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
20.07.2010
|
Online Access | Get full text |
Cover
Loading…
Abstract | The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f calculates (the count value IC+the Carry+the positive integer A). The second integer counter for generating the second clock f (f=f*G) calculates (the count value IC+the Carry+the positive integer A+the offset value) at each input clock. The correction circuit outputs the offset value so that the second integer counter counts "the maximum count value*(f/f−1)*D" times more than the first integer counter with respect to each cycle D having a synchronization cycle length of the first clock f and the second clock f |
---|---|
AbstractList | The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f calculates (the count value IC+the Carry+the positive integer A). The second integer counter for generating the second clock f (f=f*G) calculates (the count value IC+the Carry+the positive integer A+the offset value) at each input clock. The correction circuit outputs the offset value so that the second integer counter counts "the maximum count value*(f/f−1)*D" times more than the first integer counter with respect to each cycle D having a synchronization cycle length of the first clock f and the second clock f |
Author | Tsuchida, Toshiyuki Komatsu, Yoshikazu |
Author_xml | – sequence: 1 givenname: Toshiyuki surname: Tsuchida fullname: Tsuchida, Toshiyuki – sequence: 2 givenname: Yoshikazu surname: Komatsu fullname: Komatsu, Yoshikazu |
BookMark | eNrjYmDJy89L5WSQDs5Mz0vMUSgoyk9OLS7OzEtXSCwoSCxKLCkt5mFgTUvMKU7lhdLcDApuriHOHrqlxQWJJal5JcXx6UWJIMrA3NzMwMDA0JgIJQBFjyZE |
ContentType | Patent |
CorporateAuthor | NEC Electronics Corporation |
CorporateAuthor_xml | – name: NEC Electronics Corporation |
DBID | EFH |
DatabaseName | USPTO Issued Patents |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EFH name: USPTO Issued Patents url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
ExternalDocumentID | 07760001 |
GroupedDBID | EFH |
ID | FETCH-uspatents_grants_077600013 |
IEDL.DBID | EFH |
IngestDate | Sun Mar 05 22:33:27 EST 2023 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-uspatents_grants_077600013 |
OpenAccessLink | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7760001 |
ParticipantIDs | uspatents_grants_07760001 |
PatentNumber | 7760001 |
PublicationCentury | 2000 |
PublicationDate | 20100720 |
PublicationDateYYYYMMDD | 2010-07-20 |
PublicationDate_xml | – month: 07 year: 2010 text: 20100720 day: 20 |
PublicationDecade | 2010 |
PublicationYear | 2010 |
References | (99/03207) 19990100 (2006-180005) 20060700 Schowe et al. (5355502) 19941000 (09-130636) 19970500 Langendorf (5256994) 19931000 (2000-350119) 20001200 (2003-087229) 20030300 |
References_xml | – year: 20030300 ident: 2003-087229 – year: 19941000 ident: 5355502 contributor: fullname: Schowe et al. – year: 20060700 ident: 2006-180005 – year: 20001200 ident: 2000-350119 – year: 19931000 ident: 5256994 contributor: fullname: Langendorf – year: 19970500 ident: 09-130636 – year: 19990100 ident: 99/03207 |
Score | 2.7798479 |
Snippet | The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a... |
SourceID | uspatents |
SourceType | Open Access Repository |
Title | Signal processing apparatus |
URI | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7760001 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSU5KsUhLTEzTNUwzN9E1MUk21bVINTPTtUw2MDFJMjJNMgDfn-LrZ-YRauIVYRrBxOAB3wuTC8xGugVAtxTrlRYXlOSDF1cCi3dIxOtCDn8GnRGYBzp9oDwvJz8xJSAlTd8cNMME2sjFbGEAWtrn6ubBzcAJNALYZMsrKUaqNNwEGdgCwKJCDEypeSIM0sGZ6cBYUyiALM0HVhkKiQXgk7dLi0UZFNxcQ5w9dOEmxacXgVaoxBtAbTQWY2AB9tRTJRgUUhMNk0CXd1gapgF9nWxsaWJpYWZpaJwErHeB_dBESQZJnMZI4ZGTZuCCTFqbAxO1DANLSVFpqiywLixJkgN7FAB8jGjB |
link.rule.ids | 230,309,783,805,888,64367 |
linkProvider | USPTO |
linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSU5KsUhLTEzTNUwzN9E1MUk21bVINTPTtUw2MDFJMjJNMgDfn-LrZ-YRauIVYRrBxOAB3wuTC8xGugVAtxTrlRYXlOSDF1cCi3dIxOtCDn8GnRGYBzp9oDwvJz8xJSAlTd8cNMME2sjFCqxjzcBdMjcPbgZOoCHARlteSTFSteEmyMAWABYVYmBKzRNhkA7OTAfGm0IBZHE-sNJQSCwAn71dWizKoODmGuLsoQs3KT69CLRGJd4AaqexGAMLsK-eKsGgkJpomAS6vsPSMA3o72RjSxNLCzNLQ-MkYM0L7IkmSjJI4jRGCo-cPANHgItbvI-nn7c0AxdkBtscmMJlGFhKikpTZYEVY0mSHNjPANKxa74 |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Signal+processing+apparatus&rft.inventor=Tsuchida%2C+Toshiyuki&rft.inventor=Komatsu%2C+Yoshikazu&rft.number=7760001&rft.date=2010-07-20&rft.externalDBID=n%2Fa&rft.externalDocID=07760001 |