Signal processing apparatus
The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f calculates (the count value IC+the Carry+t...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
20.07.2010
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| Online Access | Get full text |
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| Summary: | The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f calculates (the count value IC+the Carry+the positive integer A). The second integer counter for generating the second clock f (f=f*G) calculates (the count value IC+the Carry+the positive integer A+the offset value) at each input clock. The correction circuit outputs the offset value so that the second integer counter counts "the maximum count value*(f/f−1)*D" times more than the first integer counter with respect to each cycle D having a synchronization cycle length of the first clock f and the second clock f |
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