Trench gate semiconductor with NPN junctions beneath shallow trench isolation structures
A trench gate semiconductor device, which is capable of securing a sufficient margin for a photo process while achieving an enhancement in gate-source leakage characteristics, is disclosed. Embodiments relate to a trench gate semiconductor device including an oxide film buffer filling a trench in an...
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| Format | Patent |
| Language | English |
| Published |
11.05.2010
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| Online Access | Get full text |
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| Summary: | A trench gate semiconductor device, which is capable of securing a sufficient margin for a photo process while achieving an enhancement in gate-source leakage characteristics, is disclosed. Embodiments relate to a trench gate semiconductor device including an oxide film buffer filling a trench in an upper surface of an epitaxial layer over a semiconductor substrate; a gate poly formed in a gate trench, the gate trench extending from the oxide film buffer to the epitaxial layer; NPN junctions formed beneath the oxide film buffer at opposite sides of the gate poly; and poly plugs to electrically connect P type portions of the NPN junctions to upper metal electrodes. |
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