Monitoring cool-down stress in a flip chip process using monitor solder bump structures

A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are...

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Bibliographic Details
Main Authors Carey, Charles F, Hansen, Bernt Julius, Malhotra, Ashwani K, Questad, David L, Sauter, Wolfgang
Format Patent
LanguageEnglish
Published 09.03.2010
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Summary:A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.