Reconfigurable high performance texture pipeline with advanced filtering

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is nee...

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Bibliographic Details
Main Authors Minkin, Alexander L, McCormack, Joel J, Heckbert, Paul S, Toksvig, Michael J. M, Chang, Luke Y, Abdalla, Karim, Hong, Bo, Berendsen, John W, Donovan, Walter, Kilgariff, Emmett M
Format Patent
LanguageEnglish
Published 19.01.2010
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Summary:Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.