Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design
A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and p...
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Main Authors | , , , , , |
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Format | Patent |
Language | English |
Published |
05.01.2010
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Online Access | Get full text |
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