Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design

• Main Authors: Arsovski, Igor, Bueti, Serafino, Iadanza, Joseph A, Norman, Jason M, Shah, Hemen R, Ventrone, Sebastian T
• Format: Patent
• Language: English
• Published: 05.01.2010

A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.