Reducing input capacitance of high speed integrated circuits

An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.

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Bibliographic Details
Main Authors Zeng, Xiang Yin, Cui, Ming Dong, Christensen, Gregory V, Abdulla, Mostafa Naguib, Lu, Daoqiang, He, Jiangqi, Tang, Jiamiao
Format Patent
LanguageEnglish
Published 19.05.2009
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Summary:An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.