Column address enable signal generation circuit for semiconductor memory device
A semiconductor memory device includes a clock period detector, a column address enable signal generator, and a multiplexing circuit. The clock period detector detects a period of an external clock in response to a pulse width information signal having a pulse width corresponding to that of the exte...
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| Format | Patent |
| Language | English |
| Published |
31.03.2009
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| Online Access | Get full text |
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| Summary: | A semiconductor memory device includes a clock period detector, a column address enable signal generator, and a multiplexing circuit. The clock period detector detects a period of an external clock in response to a pulse width information signal having a pulse width corresponding to that of the external clock. The column address enable signal generator generates a column address enable signal activated in response to a column access signal. The multiplexing circuit multiplexes points of time of inactivation of the column access signal in response to the detected signal outputted from the clock period detector. |
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