Single event upset in SRAM cells in FPGAs with high resistivity gate structures

SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodim...

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Bibliographic Details
Main Authors Voogel, Martin L, Lesea, Austin H, Fabula, Joseph J, Carmichael, Carl H, Toutounchi, Shahin, Hart, Michael J, Young, Steven P, Look, Kevin T, de Jong, Jan L
Format Patent
LanguageEnglish
Published 18.11.2008
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Summary:SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.