Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)

The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipo...

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Bibliographic Details
Main Authors Rana, Amar Pal Singh, Singh, Nirmal
Format Patent
LanguageEnglish
Published 30.09.2008
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Summary:The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.