Alignment of memory read data and clocking

Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows vario...

Full description

Saved in:
Bibliographic Details
Main Author Silvestri, Paul A
Format Patent
LanguageEnglish
Published 05.08.2008
Online AccessGet full text

Cover

More Information
Summary:Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.