CML delay cell with linear rail-to-rail tuning range and constant output swing

0pN nNnNpN 0N 0 A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a c...

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Bibliographic Details
Main Authors Cranford, Jr, Hayden C, Kossel, Marcel A, Morf, Thomas E
Format Patent
LanguageEnglish
Published 22.07.2008
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Summary:0pN nNnNpN 0N 0 A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βand a second plurality of transistors having a transconductance β, wherein respective ratios of β/βdetermine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources Mthat supply additional currents to the current source Iat a drain node of the third transistor.