Method and apparatus for staggering execution of an instruction

A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store...

Full description

Saved in:
Bibliographic Details
Main Authors Roussel, Patrice, Hinton, Glenn J, Thakkar, Shreekant S, Boswell, Brent R, Menezes, Karol F
Format Patent
LanguageEnglish
Published 29.04.2008
Online AccessGet full text

Cover

More Information
Summary:A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.