Methods, architectures, circuits and systems for transmission error determination
Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a ze...
Saved in:
Main Author | |
---|---|
Format | Patent |
Language | English |
Published |
01.04.2008
|
Online Access | Get full text |
Cover
Loading…
Abstract | Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption. |
---|---|
AbstractList | Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption. |
Author | Barash, Dror |
Author_xml | – sequence: 1 givenname: Dror surname: Barash fullname: Barash, Dror |
BookMark | eNqNjD0KAkEMRqfQwr875AAKwqxoL4qNhWAvYSbrBtyMJJnC2zuFB7B6fI_HNw8TKUKzcLuSDyXbGlDTwE7Jq1KbiTVVdgOUDPYxp9GgLwquKDayGRcBUm0qk5OOLOjNLcO0x5fR6sdFgPPpfrxsqr3RSdwez3bRsN3HXey6Q_wj-QIlETtJ |
ContentType | Patent |
CorporateAuthor | Marvell Semiconductor Israel Ltd |
CorporateAuthor_xml | – name: Marvell Semiconductor Israel Ltd |
DBID | EFH |
DatabaseName | USPTO Issued Patents |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EFH name: USPTO Issued Patents url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
ExternalDocumentID | 07353448 |
GroupedDBID | EFH |
ID | FETCH-uspatents_grants_073534483 |
IEDL.DBID | EFH |
IngestDate | Sun Mar 05 22:33:02 EST 2023 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-uspatents_grants_073534483 |
OpenAccessLink | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7353448 |
ParticipantIDs | uspatents_grants_07353448 |
PatentNumber | 7353448 |
PublicationCentury | 2000 |
PublicationDate | 20080401 |
PublicationDateYYYYMMDD | 2008-04-01 |
PublicationDate_xml | – month: 04 year: 2008 text: 20080401 day: 01 |
PublicationDecade | 2000 |
PublicationYear | 2008 |
References | Dror Barash; "Methods, Architectures, Circuits, Software and Systems for CRC Determination"; U.S. Appl. No. 10/794,496, filed Mar. 3, 2004. Zook (5724368) 19980300 Prestera-FX930 data sheet, from www.marvell.com; Marvell International, Sunnyvale, CA. Dror Barash; "Methods, Circuits, Architectures, Software and Systems for Determining a Data Transmission Error and/or Checking or Confirming Such Error Determinations"; U.S. Appl. No. 10/795,003, filed Mar. 3, 2004. Chris Borrelli; IEEE 802.3 Cyclic Redundancy Check; Mar. 23, 2001; 8 Pages; XAPP209 (v1.0); XILINX. Marvell press release, Apr. 29, 2002; www.marvell.com/press/pressNewsDisplay.do?releaseID=46. Boyer et al. (5410546) 19950400 Dubey et al. (6223320) 20010400 Kurobe et al. (6233251) 20010500 Westby (6324669) 20011100 Marvell press release, Jun. 23, 2003; www.marvell.com/press/pressNewsDisplay.do?releaseID=362. Prestera-FX902 data sheet, from www.marvell.com; Marvell International, Sunnyvale, CA. Maki (6370667) 20020400 Christensen et al. (5951707) 19990900 Prestera-FX9130 data sheet, from www.marvell.com; Marvell International, Sunnyvale, CA. DesJardins et al. (6029186) 20000200 Suzui et al. (2001/0037481) 20011100 Prestera-FX900 data sheet, from www.marvell.com; Marvell International, Sunnyvale, CA. (WO 02/093753) 20021100 Prestera-FX9110/FX9210 data sheet, from www.marvell.com; Marvell International, Sunnyvale, CA. Nakakita et al. (6061820) 20000500 Greenwood et al. (6598200) 20030700 |
References_xml | – year: 19990900 ident: 5951707 contributor: fullname: Christensen et al. – year: 20021100 ident: WO 02/093753 – year: 20011100 ident: 6324669 contributor: fullname: Westby – year: 20020400 ident: 6370667 contributor: fullname: Maki – year: 20000500 ident: 6061820 contributor: fullname: Nakakita et al. – year: 20030700 ident: 6598200 contributor: fullname: Greenwood et al. – year: 20010400 ident: 6223320 contributor: fullname: Dubey et al. – year: 20011100 ident: 2001/0037481 contributor: fullname: Suzui et al. – year: 19980300 ident: 5724368 contributor: fullname: Zook – year: 20010500 ident: 6233251 contributor: fullname: Kurobe et al. – year: 19950400 ident: 5410546 contributor: fullname: Boyer et al. – year: 20000200 ident: 6029186 contributor: fullname: DesJardins et al. |
Score | 2.704931 |
Snippet | Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the... |
SourceID | uspatents |
SourceType | Open Access Repository |
Title | Methods, architectures, circuits and systems for transmission error determination |
URI | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7353448 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NS8MwFH9sQ9CdFBXnFzl4NNoubbOeZaUIkwkKu42-pJWBdqNJ8d_3JZ1jF80tL5A8XkjeB7_8AnAX0sVbFVJyLMIxjxIVcKTGRYEaA9Q68bSLs5ckf4-eF_GiB_nuLcwXHSO-IV3MQ2s2du3BlXS9dxvPO_JnxxFYO_aB7_pzXei5rh6liAWlGn3oTwIH7Zpm-RAOaQoK2Wpr9pxGdgwHcy89gV5Zn8LrzH_WbO7ZfvGeumrVqHZlDaOknnXMyoZRLMms8yO0D66gxcqmIZH-Ra84e54By6ZvTznfrb_8aByuZRls9RTnMKD8vrwAplKUaZJWQYhppMoIZRhXehJLFAqFHI9g9Oc0l_-MXcFRB25wMJNrGNimLW_Ig1q89eb5AbQJf64 |
link.rule.ids | 230,309,786,808,891,64394 |
linkProvider | USPTO |
linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8QwEB7WVXycFBXXZw4ejbabtrFn3VIfu1RQ2FtpHpUF7S5Nin_fSavLXjS3TCAZJiTz4MsXgEsfL96y4JyKwh_SIJIeFdgoK4QSnlAqamkXx5MofQsep-G0B-nyLcwnHiO6QF3MdWMWdt6CK_F67zaeduTPjiOwcuwDX9XHvFCZKm84CxmmGmuw7nysY9EfJekObOEkGLRV1qy4jWQXNrJWugc9Xe3Dy7j9rtlckdXyPXblrJbNzBqCaT3puJUNwWiSWOdJcCdcSYvoukaR-sWvOIseAElGr3cpXa6fv9cO2ZJ7P5qyQ-hjhq-PgMhY8DiKS88XcSB1ILgfluo25IJJwfhwAIM_pzn-Z-wCNrP7JH9-mDydwHaHdHCYk1Po27rRZ-hOrThvLfUNHE6CqA |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Methods%2C+architectures%2C+circuits+and+systems+for+transmission+error+determination&rft.inventor=Barash%2C+Dror&rft.number=7353448&rft.date=2008-04-01&rft.externalDBID=n%2Fa&rft.externalDocID=07353448 |