Methods, architectures, circuits and systems for transmission error determination
Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a ze...
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| Format | Patent |
| Language | English |
| Published |
01.04.2008
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| Online Access | Get full text |
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| Summary: | Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption. |
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