Method of making a semiconductor structure with a plating enhancement layer

Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed b...

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Bibliographic Details
Main Authors Ponoth, Shom, Chen, Steven Shyng-Tsong, Fitzsimmons, John Anthony, Spooner, Terry Allen
Format Patent
LanguageEnglish
Published 11.03.2008
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Summary:Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.