Semiconductor device

A dummy cell includes a plurality of first memory cells MC for storing "1" or "0", arranged at points of intersection between a plurality of word lines WR to WR and a plurality of first data lines D to D a plurality of first dummy cells MCH for storing "1" or "0&qu...

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Bibliographic Details
Main Authors Hanzawa, Satoru, Sakata, Takeshi
Format Patent
LanguageEnglish
Published 23.10.2007
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Summary:A dummy cell includes a plurality of first memory cells MC for storing "1" or "0", arranged at points of intersection between a plurality of word lines WR to WR and a plurality of first data lines D to D a plurality of first dummy cells MCH for storing "1" or "0", arranged at points of intersection between the word lines WR to WR and a first dummy data line, and a plurality of second dummy cells MCL for storing "0", arranged at points of intersection between the word lines WR to WR and a second dummy data line DD