System and method for verifying signal propagation delays of circuit traces of a PCB layout

A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer. The computer includes: a setting module for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding...

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Main Authors Tsai, Hung-Yuan, Tong, Mo-Ying
Format Patent
LanguageEnglish
Published 16.10.2007
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Abstract A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer. The computer includes: a setting module for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding whether to calculate a propagation delay of a lead wire connected with the trace; a selecting module for selecting a segment from a segment set of the trace; a calculating module for calculating a propagation delay of the segment, the trace and the lead wire, and a total propagation delay; and a determining module for determining whether all segments of the trace have been calculated, and whether the total propagation delay is between the minimum propagation delay and the maximum propagation delay. A related method is also disclosed.
AbstractList A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer. The computer includes: a setting module for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding whether to calculate a propagation delay of a lead wire connected with the trace; a selecting module for selecting a segment from a segment set of the trace; a calculating module for calculating a propagation delay of the segment, the trace and the lead wire, and a total propagation delay; and a determining module for determining whether all segments of the trace have been calculated, and whether the total propagation delay is between the minimum propagation delay and the maximum propagation delay. A related method is also disclosed.
Author Tong, Mo-Ying
Tsai, Hung-Yuan
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Hon Hai Precision Industry Co., Ltd
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References Iwanishi (6718529) 20040400
Voloshin et al. (7061931) 20060600
Devadas et al. (2006/0221686) 20061000
Lin (6349402) 20020200
Chang et al. (6415426) 20020700
Brooks et al. (2004/0207064) 20041000
Arkas et al. (6696875) 20040200
Chang et al. (5610833) 19970300
Arkas et al. (2004/0135613) 20040700
Barnette et al. (6316944) 20011100
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Snippet A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer. The computer includes: a...
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Title System and method for verifying signal propagation delays of circuit traces of a PCB layout
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