System and method for verifying signal propagation delays of circuit traces of a PCB layout
A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer. The computer includes: a setting module for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
16.10.2007
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| Online Access | Get full text |
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| Summary: | A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer. The computer includes: a setting module for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding whether to calculate a propagation delay of a lead wire connected with the trace; a selecting module for selecting a segment from a segment set of the trace; a calculating module for calculating a propagation delay of the segment, the trace and the lead wire, and a total propagation delay; and a determining module for determining whether all segments of the trace have been calculated, and whether the total propagation delay is between the minimum propagation delay and the maximum propagation delay. A related method is also disclosed. |
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