Method and apparatus of optimizing the IO collar of a peripheral image
An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar. All the IO cells may be rotated,...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
04.09.2007
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Online Access | Get full text |
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