Method and apparatus of optimizing the IO collar of a peripheral image

An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar. All the IO cells may be rotated,...

Full description

Saved in:
Bibliographic Details
Main Authors Chung-Maloney, Wai Ling, Ito, Haruo, Stout, Douglas W
Format Patent
LanguageEnglish
Published 04.09.2007
Online AccessGet full text

Cover

More Information
Summary:An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar. All the IO cells may be rotated, or a combination of rotated and non-rotated IO cells may form the IO collar. For each edge of the IC chip having rotated IO cells, each edge may have the same number of stacks of IO cells or a different number of stacks of IO cells.