Volatile memory devices and methods for forming same

A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level po...

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Main Authors Hung, Chin-Long, Chang, Hong-Long, Lee, Yueh-Chuan
Format Patent
LanguageEnglish
Published 10.07.2007
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Abstract A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
AbstractList A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
Author Lee, Yueh-Chuan
Chang, Hong-Long
Hung, Chin-Long
Author_xml – sequence: 1
  givenname: Chin-Long
  surname: Hung
  fullname: Hung, Chin-Long
– sequence: 2
  givenname: Hong-Long
  surname: Chang
  fullname: Chang, Hong-Long
– sequence: 3
  givenname: Yueh-Chuan
  surname: Lee
  fullname: Lee, Yueh-Chuan
BookMark eNrjYmDJy89L5WQwCcvPSSzJzElVyE3NzS-qVEhJLctMTi1WSMxLAQqVZOSnFCuk5ReBcG5mXrpCcWJuKg8Da1piTnEqL5TmZlBwcw1x9tAtLS5ILEnNKymOTy9KBFEG5kYmhmamlsZEKAEA_9wvbQ
ContentType Patent
CorporateAuthor Promos Technologies, Inc
CorporateAuthor_xml – name: Promos Technologies, Inc
DBID EFH
DatabaseName USPTO Issued Patents
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EFH
  name: USPTO Issued Patents
  url: http://www.uspto.gov/patft/index.html
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
ExternalDocumentID 07241659
GroupedDBID EFH
ID FETCH-uspatents_grants_072416593
IEDL.DBID EFH
IngestDate Sun Mar 05 22:31:31 EST 2023
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-uspatents_grants_072416593
OpenAccessLink https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7241659
ParticipantIDs uspatents_grants_07241659
PatentNumber 7241659
PublicationCentury 2000
PublicationDate 20070710
PublicationDateYYYYMMDD 2007-07-10
PublicationDate_xml – month: 07
  year: 2007
  text: 20070710
  day: 10
PublicationDecade 2000
PublicationYear 2007
References Hieda et al. (5736760) 19980400
Chen et al. (6987044) 20060100
References_xml – year: 20060100
  ident: 6987044
  contributor:
    fullname: Chen et al.
– year: 19980400
  ident: 5736760
  contributor:
    fullname: Hieda et al.
Score 2.6775427
Snippet A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar...
SourceID uspatents
SourceType Open Access Repository
Title Volatile memory devices and methods for forming same
URI https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7241659
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1NT8MwDLW2CQk4gQAxPqYcuAbakaTpGa2qJg3tAGi3KW0Ml7Wdlk5o_x4nhYkLHHJxJMdKZD87enEA7jShjoww5j72cTEuBU-1LniZkCAgVOgzO3tW-auYLuSiB_n-LUxFbsTXZIu737p12wRyJYX37uB51_zZ9wisffeBz3rVGDu37w8JQZGSaR_6OvLUvkmWH8MhqaCUrW7dL9DITuBgHqSn0MP6DMRb43lnK2SVZ7fumMXgpYxqedZ95OwYpZB-VAQozJkKz4Flk5ennO-XWH5sPHVlGX2b8ngBAyrh8RKYQBVThDM2salQRurYIBUahZJjVWqTDGH4p5qrf-au4ejnrjGObmDQbrZ4SyDZFqOwA1-gNXFb
link.rule.ids 230,309,783,805,888,64367
linkProvider USPTO
linkToPdf http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV07T8MwED6VgnhMIEC0vDywGpJiO84MROFVZQDULXJiw9IkVZ0K8e97dqBigcHLWTqfbN1991nnM8CFRNThgQmpi32UjUpGYykLWkYo8Ajl-8w-j0X6yh4mfNKDdPUWpkI3ojO0xV4u7KxtfHElhvfu4GnX_Nn1CKxd94HPetoonen3qwihSPB4DdYRY4WnZEm6A1uoBJO2urW_YCPZhY3MS_egZ-p9YG-NqzybGlK5-tYvoo33U4JsnnRfOVuCSaQbFUIKsaoyB0CSu5eblK6WyD_mrnglD76NuT6EPpJ4cwSEGRFijFM60jETistQGaQaheAjUUoVDWDwp5rhP3PnsJndJvnT_fjxGLZ_Lh7D4AT67XxhThEx2-LMb8YSXHd0WA
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Volatile+memory+devices+and+methods+for+forming+same&rft.inventor=Hung%2C+Chin-Long&rft.inventor=Chang%2C+Hong-Long&rft.inventor=Lee%2C+Yueh-Chuan&rft.number=7241659&rft.date=2007-07-10&rft.externalDBID=n%2Fa&rft.externalDocID=07241659