Random generator description

A pseudo random generator comprising a shift register comprising a first flip flop (F) and n further flip-flops (F . . . Fn) each flip-flop (F) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F) having a set input, each of the n...

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Bibliographic Details
Main Authors Van Veldhoven, Robert Henrikus Margaretha, Hoogzaad, Gian
Format Patent
LanguageEnglish
Published 26.06.2007
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Summary:A pseudo random generator comprising a shift register comprising a first flip flop (F) and n further flip-flops (F . . . Fn) each flip-flop (F) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F) having a set input, each of the non-inverting outputs being connected via a NOR gate to the set input of the first flip-flop (F) and each of the non-inverting outputs of the flip-flops (F . . . Fn) being connected to the input of the first flip-flop (F) via an XOR gate, characterised in that the generator comprises at least one additional logic gate including at least one additional flip-flop.The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra '0' at the output or to chop, preferably randomly, the input signal.